1. Field of the Invention
This invention relates to a data processing device, and more particularly, to a device for processing a plurality of transmitted data blocks each including a synchronizing data and an address data.
2. Description of the Prior Art
Generally, a system for transmitting data sequences including information data is required to perform such processes as the correction of errors in codes, and the arrangement of information data after transmission, such as recording or reproduction. Thus, the transmitted data must be first stored in a memory such as a random access memory (RAM). At that time, all of the data must be stored into predetermined positions in the memory in accordance with address data which is provided in front of them.
However, since the address data is also to be transmitted in the same manner as the information data, they are subject to some code errors due to drop-out, jitter, intersymbol interference, etc. Therefore, it is not always safe to have the information data stored in the memory solely in accordance with the transmitted address data. In view of this, it has been known to generate data similar to the address data by counting the synchronizing data included in each of the data blocks simultaneously with the address data. In other words, the data storing positions in the memory are determined by means of a counter, called an internal address counter. However, since this method is to be carried out by counting the synchronizing data, which is also transmsitted, a count value obtainable in this method is also subject to error due to possible drop-out of the synchronizing data, noise, etc. It is especially a serious drawback of this method that, once the synchronizing data is miscounted, the ensuing data will all become invalid.